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1

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 22 February 2015)] Design-Process-Technology Co-optimization for Manufacturability IX - Layout dependent effects analysis on 28nm process

Sturtevant, John L., Capodieci, Luigi, Li, Helen, Zhang, Mealie, Wong, Waisum, Song, Huiyuan, Xu, Wei, Hurat, Philippe, Ding, Hua, Zhang, Yifan, Cote, Michel, Huang, Jason, Lai, Ya-ch

Year:

2015

Language:

english

File:

PDF, 433 KB

english, 2015

2

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California (Sunday 12 February 2012)] Design for Manufacturability through Design-Process Integration VI - Electrical design for manufacturability and lithography and stress variability hotspot detection flows at 28nmn

Hurat, Philippe, Zhu, Jianhao, Teoh, Edward, Mason, Mark E.

Year:

2012

Language:

english

File:

PDF, 802 KB

english, 2012

3

[IEEE Comput. Soc 5th International Symposium on Quality Electronic Design - San Jose, CA, USA (22-24 March 2004)] SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720) - Layout printability optimization using a silicon simulation methodology

Cote, M., Hurat, P.

Year:

2004

Language:

english

File:

PDF, 532 KB

english, 2004

4

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 27 February 2011)] Design for Manufacturability through Design-Process Integration V - Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs

Hurat, Philippe, Rieger, Michael L., Topaloglu, Rasit O., Nachman, Ramez, Pathak, Piyush, Condella, Jac, Madhavan, Sriram, Capodieci, Luigi

Year:

2011

Language:

english

File:

PDF, 3.76 MB

english, 2011

5

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California (Sunday 12 February 2012)] Design for Manufacturability through Design-Process Integration VI - Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs

Wang, Yangang, Zwolinski, Mark, Appleby, Andrew, Scoones, Mark, Caldwell, Sonia, Azam, Touqeer, Hurat, Philippe, Pitchford, Chris, Mason, Mark E.

Year:

2012

Language:

english

File:

PDF, 844 KB

english, 2012

6

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 22 February 2009)] Design for Manufacturability through Design-Process Integration III - Layout electrical cooptimization for increased tolerance to process variations

Riviere-Cazaux, Lionel, Singh, Vivek K., Rieger, Michael L., Hurat, Philippe, Kasthuri, Bala, Layton, Larry, Verghese, Nishath

Year:

2009

Language:

english

File:

PDF, 294 KB

english, 2009

7

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California (Sunday 12 February 2012)] Design for Manufacturability through Design-Process Integration VI - In-design process hotspot repair using pattern matching

Jang, Daehyun, Ha, Naya, Jeon, Junsu, Kang, Jae-Hyun, Paek, Seung Weon, Choi, Hungbok, Kim, Kee Sup, Lai, Ya-Chieh, Hurat, Philippe, Luo, Wilbur, Mason, Mark E.

Year:

2012

Language:

english

File:

PDF, 12.89 MB

english, 2012

8

[IEEE 2019 Electron Devices Technology and Manufacturing Conference (EDTM) - Singapore, Singapore (2019.3.12-2019.3.15)] 2019 Electron Devices Technology and Manufacturing Conference (EDTM) - High Performance Full Chip Device Profiling and DOE selection for Physical and Parametric Yield Monitoring

Lai, Ya-Chieh, Salem, Rami, Pinto, Angelo, Cote, Michel, Xu, Wei, Pathak, Piyush, Hurat, Philippe

Year:

2019

Language:

english

File:

PDF, 122 KB

english, 2019

9

The Empirical Watershed Wavelet

Hurat, Basile, Alvarado, Zariluz, Gilles, JÃ©rÃ´me

Journal:

Journal of Imaging

Year:

2020

File:

PDF, 3.40 MB

2020

10

[IEEE Comput. Soc. Press [1989] International Conference on Wafer Scale Integration - San Francisco, CA, USA (3-5 Jan. 1989)] [1989] Proceedings International Conference on Wafer Scale Integration - A reconfigurable WSI neural network

Blayo, F., Hurat, P.

Year:

1989

Language:

english

File:

PDF, 516 KB

english, 1989

11

[IEEE Computer Soc 18th International Conference on VLSI Design - Kolkata, India (3-7 Jan. 2005)] 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design - DFM: linking design and manufacturing

Raghvendra, S., Hurat, P.

Year:

2005

Language:

english

File:

PDF, 359 KB

english, 2005

12

[IEEE IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium - San Jose, CA, USA (14-16 July 2004)] IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585) - How can design for manufacturing improve mask cost and yield?

Cote, M., Hurat, P., Rieger, M., Miloslavsky, A., Goinard, D.

Year:

2004

Language:

english

File:

PDF, 402 KB

english, 2004

13

[IEEE 2008 Asia and South Pacific Design Automation Conference (ASPDAC) - Seoul, South Korea (2008.03.21-2008.03.24)] 2008 Asia and South Pacific Design Automation Conference - Predictive models and CAD methodology for pattern dependent variability

Verghese, Nishath, Rouse, Richard, Hurat, Philippe

Year:

2008

Language:

english

File:

PDF, 283 KB

english, 2008

14

[IEEE 2007 IEEE Custom Integrated Circuits Conference - San Jose, CA, USA (2007.09.16-2007.09.19)] 2007 IEEE Custom Integrated Circuits Conference - Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices

Devoivre, Thierry, Rouse, Richard, Verghese, Nishath, Hurat, Philippe

Year:

2007

Language:

english

File:

PDF, 552 KB

english, 2007

15

[IEEE Sixth International Symposium on Quality of Electronic Design (ISQED'05) - San Jose, CA, USA (21-23 March 2005)] Sixth International Symposium on Quality of Electronic Design (ISQED'05) - Standard Cell Printability Grading and Hot Spot Detection

Cote, M., Hurat, P.

Year:

2005

Language:

english

File:

PDF, 328 KB

english, 2005

16

[IEEE 2007 IEEE Custom Integrated Circuits Conference - San Jose, CA, USA (2007.09.16-2007.09.19)] 2007 IEEE Custom Integrated Circuits Conference - Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design

Wang, Pei-Hua, Lee, Brian, Han, Gus, Rouse, Richard, Hurat, Philippe, Verghese, Nishath

Year:

2007

Language:

english

File:

PDF, 502 KB

english, 2007

17

[IEEE 2007 Asia and South Pacific Design Automation Conference - Yokohama, Japan (2007.01.23-2007.01.26)] 2007 Asia and South Pacific Design Automation Conference - DFM reality in sub-nanometer IC design

Verghese, Nishath, Hurat, Philippe

Year:

2007

Language:

english

File:

PDF, 5.93 MB

english, 2007

18

[IEEE 2007 IEEE International SOC Conference (SOCC) - Hsin Chu, Taiwan (2007.09.26-2007.09.29)] 2007 IEEE International SOC Conference - Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability

Tsiena, Darsun, Chien Kuo Wang,, Wang, William W.J., Yajun Ran,, Hurat, Philippe, Verghese, Nishath

Year:

2007

Language:

english

File:

PDF, 381 KB

english, 2007

19

[ACM Press the 38th conference - Las Vegas, Nevada, United States (2001..-..)] Proceedings of the 38th conference on Design automation - DAC '01 - Practical application of full-feature alternating phase-shifting technology for a phase-aware standard-cell design flow

Sanie, Michael, Côté, Michel, Hurat, Philippe, Malhotra, Vinod

Year:

2001

Language:

english

File:

PDF, 1.24 MB

english, 2001

20

SPIE Proceedings [SPIE Advanced Lithography - San Jose, CA (Sunday 25 February 2007)] Design for Manufacturability through Design-Process Integration - Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability

Tsien, Darsun, Wang, Chien Kuo, Ran, Yajun, Hurat, Philippe, Verghese, Nishath, Wong, Alfred K. K., Singh, Vivek K.

Year:

2007

Language:

english

File:

PDF, 503 KB

english, 2007

21

SPIE Proceedings [SPIE Advanced Lithography - San Jose, CA (Sunday 25 February 2007)] Design for Manufacturability through Design-Process Integration - Model-based approach for design verification and co-optimization of catastrophic and parametric-related defects due to systematic manufacturing variations

Perry, Dan, Nakamoto, Mark, Verghese, Nishath, Hurat, Philippe, Rouse, Rich, Wong, Alfred K. K., Singh, Vivek K.

Year:

2007

Language:

english

File:

PDF, 425 KB

english, 2007

22

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, CA (Sunday 22 February 2009)] Design for Manufacturability through Design-Process Integration III - Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

Sadra, Kayvan, Terry, Mark, Rajagopal, Arjun, Soper, Robert A., Kolarik, Donald, Aton, Tom, Hornung, Brian, Khamankar, Rajesh, Hurat, Philippe, Kasthuri, Bala, Ran, Yajun, Verghese, Nishath, Singh, Vi

Year:

2009

Language:

english

File:

PDF, 257 KB

english, 2009

23

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California (Sunday 21 February 2010)] Design for Manufacturability through Design-Process Integration IV - Foundry verification of IP and incoming designs for manufacturing variability

Chang, Li-Fu, Rieger, Michael L., Thiele, Joerg, Fu, Julia, Yang, Josh, Zou, Elain, Hurat, Philippe, Verghese, Nishath, Ding, Hua

Year:

2010

Language:

english

File:

PDF, 627 KB

english, 2010

24

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 27 February 2011)] Design for Manufacturability through Design-Process Integration V - Applying litho-aware timing analysis to hold time fixing reduces design cycle time and power dissipation

Hirabayashi, Keisuke, Rieger, Michael L., Kobayashi, Naohiro, Mizuno, Hidemichi, Onodera, Tomoo, Oguro, Tsuyoshi, Hurat, Philippe, Chatterjee, Arindam, Seki, Koichi

Year:

2011

Language:

english

File:

PDF, 563 KB

english, 2011

25

Infill Drilling in the Rotherwood Field, Harris County, Texas

Journal:

SPE Reservoir Engineering

Year:

1991

Language:

english

File:

PDF, 767 KB

english, 1991

26

SPIE Proceedings [SPIE SPIE 31st International Symposium on Advanced Lithography - San Jose, CA (Sunday 19 February 2006)] Design and Process Integration for Microelectronic Manufacturing IV - A genuine design manufacturability check for designers

Hurat, Philippe, Wong, Alfred K. K., Singh, Vivek K., Cote, Michel, Tsai, Chi-Ming, Brandenburg, Joe

Year:

2006

Language:

english

File:

PDF, 272 KB

english, 2006

27

SPIE Proceedings [SPIE 27th Annual BACUS Symposium on Photomask Technology - Monterey, CA (Monday 17 September 2007)] Photomask Technology 2007 - A lithography aware design optimization using foundry-certified models and hotspot detection

Karklin, L., Naber, Robert J., Kawahira, Hiroichi, Arkhipov, A., Blakely, D., Dingenen, M., Mehrotra, A., Watson, B., Zelnik, C., Cote, M., Hurat, P.

Year:

2007

Language:

english

File:

PDF, 362 KB

english, 2007

28

SPIE Proceedings [SPIE Microlithography 2005 - San Jose, CA (Sunday 27 February 2005)] Design and Process Integration for Microelectronic Manufacturing III - Mask cost reduction and yield optimization using design intent

Cote, Michel, Liebmann, Lars W., Miloslavsky, Alexander, Hurat, Philippe, Rieger, Michael L., Goinard, Denis

Year:

2005

Language:

english

File:

PDF, 627 KB

english, 2005

29

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California (Sunday 12 February 2012)] Design for Manufacturability through Design-Process Integration VI - In-design hierarchical DFM closure for DFM-clean IP

Tripathi, Vikas, Subramanian, Jayathi, Sharma, Puneet, Chen, Kuang-Han, Kasthuri, Bala, Hurat, Philippe, Layton, Larry, Mason, Mark E.

Year:

2012

Language:

english

File:

PDF, 24.13 MB

english, 2012

30

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 27 February 2011)] Design for Manufacturability through Design-Process Integration V - In-design DFM CMP flow for block level simulation using 32nm CMP model

Ha, Naya, Rieger, Michael L., Lee, Jinwoo, Paek, S. W., Kim, Kee Sup, Chen, Kuang Han, Gower-Hall, Aaron, Gbondo-Tugbawa, Tamba, Hurat, Philippe

Year:

2011

Language:

english

File:

PDF, 634 KB

english, 2011

31

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California (Sunday 21 February 2010)] Design for Manufacturability through Design-Process Integration IV - Realizing a 45-nm system on chip in the age of variability

Le Cam, Laurent, Rieger, Michael L., Thiele, Joerg, Appleby, Andy, Hurat, Philippe, Carpentier, Benoit, Chen, Kuang-Han, Verghese, Nishath

Year:

2010

Language:

english

File:

PDF, 760 KB

english, 2010

32

SPIE Proceedings [SPIE Advanced Lithography - San Jose, CA (Sunday 25 February 2007)] Design for Manufacturability through Design-Process Integration - Automated full-chip hotspot detection and removal flow for interconnect layers of cell-based designs

Roseboom, Ed, Wong, Alfred K. K., Singh, Vivek K., Rossman, Mark, Chang, Fang-Cheng, Hurat, Philippe

Year:

2007

Language:

english

File:

PDF, 293 KB

english, 2007

33

SPIE Proceedings [SPIE Photomask Technology 2005 - Monterey, California (Monday 3 October 2005)] 25th Annual BACUS Symposium on Photomask Technology - DFM for manufacturers and designers

Hurat, Philippe, Weed, J. Tracy, Martin, Patrick M., Cote, Michel

Year:

2005

Language:

english

File:

PDF, 262 KB

english, 2005

34

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 22 February 2009)] Design for Manufacturability through Design-Process Integration III - Convergent automated chip level lithography checking and fixing at 45nm

Perez, Valerio, Singh, Vivek K., Rieger, Michael L., Quek, Shyue Fong, Yeo, Sky, Hui, Colin, Lin, Kuang Kuo, Ng, Walter, Cote, Michel, Kasthuri, Bala, Hurat, Philippe, Thompson, Matt A., Yuan, Chi-Min

Year:

2009

Language:

english

File:

PDF, 650 KB

english, 2009

35

SPIE Proceedings [SPIE Microlithography 2005 - San Jose, CA (Sunday 27 February 2005)] Design and Process Integration for Microelectronic Manufacturing III - Process centering OPC using design intent to improve yield

Cote, Michel, Liebmann, Lars W., Miloslavsky, Alexander, Lugg, Robert, Rieger, Michael L., Hurat, Philippe

Year:

2005

Language:

english

File:

PDF, 252 KB

english, 2005

36

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California (Sunday 12 February 2012)] Design for Manufacturability through Design-Process Integration VI - Analysis of layout-dependent context effects on timing and leakage in 28nm

McGuinness, Patrick, Sharma, Puneet, Hurat, Philippe, Mason, Mark E.

Year:

2012

Language:

english

File:

PDF, 1.05 MB

english, 2012

37

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 23 February 2014)] Design-Process-Technology Co-optimization for Manufacturability VIII - Layout induced variability and manufacturability checks in FinFETs process

Sturtevant, John L., Capodieci, Luigi, Ban, Yongchan, Sweis, Jason, Hurat, Philippe, Lai, Ya-Chieh, Kang, Yongseok, Paik, Woo Hyun, Xu, Wei, Song, Huiyuan

Year:

2014

Language:

english

File:

PDF, 661 KB

english, 2014

38

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 27 February 2011)] Design for Manufacturability through Design-Process Integration V - Accurately predicting copper interconnect topographies in foundry design for manufacturability flows

Lu, Daniel, Rieger, Michael L., Fan, Zhong, Tak, Ki Duk, Chang, Li-Fu, Zou, Elain, Jiang, Jenny, Yang, Josh, Zhuang, Linda, Chen, Kuang Han, Hurat, Philippe, Ding, Hua

Year:

2011

Language:

english

File:

PDF, 9.02 MB

english, 2011

39

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Optical Microlithography XXX - In-design and signoff lithography physical analysis for 7/5nm (Erratum)

Erdmann, Andreas, Kye, Jongwook, Tabery, Cyrus, Ye, Jun, Zou, Yi, Arnoux, Vincent, Raghavan, Praveen, Kim, Ryoung-han, Côté, Michel, Mattii, Luca, Lai, Ya-Chieh, Hurat, Philippe

Year:

2017

Language:

english

File:

PDF, 673 KB

english, 2017

40

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 26 February 2017)] Design-Process-Technology Co-optimization for Manufacturability XI - A fast process development flow by applying design technology co-optimization

Capodieci, Luigi, Cain, Jason P., Chen, Yi-Chieh, Yeh, Shin-Shing, Ou, Tsong-Hua, Lin, Hung-Yu, Mai, Yung-Ching, Lin, Lawrence, Lai, Jun-Cheng, Lai, Ya Chieh, Xu, Wei, Hurat, Philippe

Year:

2017

Language:

english

File:

PDF, 628 KB

english, 2017

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